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    IEEE/IEC 62530:2011

    SystemVerilog – Unified Hardware Design, Specification, and Verification Language

    Standard Details

    This standard represents a merger of two previous StandardDetails: IEEE Std 1364™-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog sta

    General Information

    Status : ACTIVE
    Standard Type: Main
    Document No: IEEE/IEC 62530:2011
    Document Year: 2011
    Pages: 1294
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    IEEE/IEC 62530:2011

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