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    IEEE 1450.6.2:2014

    IEEE Standard for Memory Modeling in Core Test Language

    Standard Details

    SoC test requires reuse of test data and test structures developed for individual cores (designs) when integrated into larger integrated circuits. This standard defines language constructs sufficient to represent the context of a memory core and of the integration of that memory core into an SoC. This facilitates the development and reuse of test and repair mechanisms for memories. This standard also defines constructs that represent the test structures internal to the memory core for reuse in the creation of the tests for the logic outside the memory core. Semantic rules are defined for the language to facilitate interoperability between different entities (the memory core provider, the system integrator, and the automation tool developer) involved in the creation of an SoC. The capabilities are an extension of IEEE Std 1450.6(TM)-2005. As a result of this extension, CTLs limitations of handling memories are addressed

    General Information

    Status : ACTIVE
    Standard Type: Main
    Document No: IEEE 1450.6.2:2014
    Document Year: 2014
    Pages: 74
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    IEEE 1450.6.2:2014

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